Traditional memory bit cells are well known and widely used. In a conventional six transistor (6T) bitcell, in order to write into the bitcell, a Write Line (WL) needs to go high and the zero is written either from the Bit Line (BL) or the Bit Line Bar (BLB) side by pulling either the BL or the BLB low depending on the data. The READ happens by sensing the differential between the BL and BLB when the WL goes high. In a conventional eight transistor (8T) bitcell the WRITE operation is same as in the 6T bitcell. The READ operation happens when the RWL goes high. The RBL is precharged high. If the node B is high, then the RBL will go low, otherwise it will stay high.
SUMMARY
In the earlier memory bitcell architectures, in order to accomplish a write to the bit cell, a write bitline, a write column mux comprised of the NMOS pass transistors, and a write driver were required. As the write driver had to drive the bitline through the write mux pass transistor, the size of the write driver needed to be bigger and the statistical analysis had to be carried out on the combination of bitline RC, write mux and the write driver. This increased the problem of writing into the bitcell and contributed to the necessity of the write-assist techniques. In accordance with the present invention, the writing into the bitcell is now made simple and local to the bitcell, and there would be many technology nodes where the necessity of the write- assist techniques will not be there. So we have also taken care of the write-assist requirement.
In the previous patents with Ser. Nos. 62/036,189 and 14/519,468, a 9T bitcell for 1R1W (One Read One Write) SRAM memories with single-ended read and single-ended write was described.
Conventional memory bit cells suffer from a number of deficiencies as recited above. Embodiments of the invention significantly overcome such deficiencies by providing a bitcell and memory architecture without a write bitline.
The U.S. Provisional patent application Ser. No. 62/098,460 filed on Dec. 31, 2014 describes 9T, 8T and 7T versions of bitcells used with SRAM memories which can be used in place of conventional bitcells. In the 9T Bitcell a WD (Wordline Driver) ships out signals WWL (Write Word Line) and RWL (Read Word Line). In the 8T Bitcell a WD (Wordline Driver) ships out signals RWL (Read Word Line) and either WWLXPD (Write Word Line Tri-statatble Pull Down) or WWLB (Write Word Line Bar). In the 7T Bitcell a WD (Wordline Driver) ships out either WWLXPD (Write Word Line Tri-statable Pull Down) or WWLB (Write Word Line Bar) and either RWLXPD (Read Word Line Tri-statable Pull Down) or RWLB (Read Word Line Bar). Different circuits are needed to support different bitcells and architectures mentioned above.
When migrating from 9T to 8T to 7T bitcells, the bitcell area reduces. Also, as the WWLB and RWLB invertors or the WWLXPD and RWLXPD transistors can be sized as per the design requirements, we can optimize the READ and WRITE performance. In summary, the proposed new bitcells and the memory architectures bring a huge improvement in the performance, dynamic power, leakage power, area, and the yield of the memory.
Note that each of the different features, techniques, configurations, etc. discussed in this disclosure can be executed independently or in combination. Accordingly, the present invention can be embodied and viewed in many different ways. Also, note that this summary section herein does not specify every embodiment and/or incrementally novel aspect of the present disclosure or claimed invention. Instead, this summary only provides a preliminary discussion of different embodiments and corresponding points of novelty over conventional techniques. For additional details, elements, and/or possible perspectives (permutations) of the invention, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.